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SR. DESIGN VERIFICATION ENGINEER

Esperanto Technologies

Esperanto Technologies

Design
Mountain View, CA, USA
Posted on Saturday, February 25, 2023

Description

Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solution, without the baggage of existing legacy architectures, or the programmability limitations of overspecialized hardware. Esperanto leverages the simple, elegant, open standard RISC-V ISA along with leading-edge system architectures to deliver flexibility, scalability, performance, and energy-efficiency advantages.

About The Role

Our Portland office is looking for enthusiastic engineers to join the CPU/IP/SoC verification team. Working closely with the local design team, you will be responsible for verifying subsystems such as caches, memories, and interconnects, as well as their integration into the larger SoC. We are looking for highly talented, self-motivated, and versatile engineers that will push hardware to the highest performance and quality standards.

Responsibilities

  • Own, develop, and drive the full verification process of SoC functional blocks
  • Create verification content including testplans, test bench components, directed and constrained random tests, and functional coverage
  • Broader responsibilities may include supporting full-chip simulation, emulation, and post-silicon bring up

Qualifications

  • Ability to clearly communicate across teams with multidisciplinary backgrounds
  • BS or MS in EE
  • 3+ years of experience in CPU, IP or SoC verification
  • Knowledge of high-level verification flow methodology (testplan development, constrained random test generation and debug, coverage analysis and closure)
  • Experience with a class-based testbench using SystemVerilog or similar language
  • Knowledge of memory coherence, DDR, AXI/ACE is required
  • Experience with UVM/OVM is required
  • Experience with C/C++ and assembly is a plus
  • Experience with Python, Perl, or other scripting languages is a plus

Benefits

  • Base salary range is $100,000 - $300,000
  • The actual salary of a successful applicant may vary from the posted range based on a candidate’s experience, training, education, location and/or other legitimate business reasons.
  • You will also be eligible for stock options and benefits.