Description

• The candidate must have hands-on experience in full chip, hierarchical, and block level STA signoff run setup and will be responsible in closing setup, hold timing and meeting timing checks for max transition, capacitance, min period, min pulse width, etc.
• The candidate will be responsible for STA flow development, setting up signoff derates, margins etc. per foundry signoff, debugging constraints, timing budgeting, debugging extraction issues, corelating place and route to timing, spice to timing, running different corner STA runs at full chip, hierarchical or block level.
• The candidate is responsible for full chip, hierarchical and block level timing closure.
• The candidate is responsible for analyzing and optimizing design constraints and synthesis parameters to achieve performance, power, and area targets.
• The candidate should be well versed in eco timing methodology and is responsible in generating and issuing timing Eco’s for full chip, hierarchical or block level to fix timing.
• Hands-on experience running Spice on the top-level clock network is a plus.
• The candidate should be able to probe timing reports, debug and collaborate closely with RTL designers to achieve timing closure and the best PPA.
• To deliver top quality chips, we must work cross-functionally. The candidate will collaborate effectively with all parts of engineering: Architecture, RTL Design and Verification.
• We are a results-driven team. The candidate should be able to adopt a data-driven approach, assess the TAT for full chip, hierarchical and block level STA runs, should periodically document the results, assess the progress and PPA improvements.
• The candidate will be mentoring junior engineers or interns and aid in knowledge sharing with a giver mindset.

• BS/MS in Electrical Engineering or equivalent.
• 10+ years of ASIC STA Timing experience closing full chip or hierarchical level timing with successful Tape-outs at the latest technology nodes (7nm experience preferred).
• Hands-on experience in ASIC timing closure at full chip or hierarchical level with a very good understanding of RTL logic design as well as physical design or circuit level skills for timing closure.
• Excellent problem solving and debugging skills for timing issues, timing constraints and clocking.
• Proficiency and hands-on usage with EDA tools: Primetime-SI, StarRC, DC, ICC2, FC, Formal.
• Expertise in STA tools and methodologies for timing closure with a good understanding of deep sub-micron process effects.
• Strong background and hands-on experience in timing constraints generation, analysis and debugging including SDCs.
• Strong knowledge of different modes, timing corners, experience with modelling process variations and resolving signal integrity related issues.
• Strong expertise in analysis and fixing of crosstalk violations due to delay variation, noise, glitch and electrical or manufacturing rules in deep-sub micron processes.
• Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and tools.
• Experience in full product life cycle from 1st Tapeout to metal spins to full silicon production.
• Proficiency in scripting using TCL, Perl, etc. and ability to understand and improve existing flows and methodologies.
• Strong engineering mindset, startup mentality, versatility, and interpersonal skills.